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AMIC110多协议可编工业通信处理器开发方案

作者:河北教育网 线上知名博彩首页 更新时间:2019年10月19日 08:38:29 游览量:200

简述:

TI公司的AM3359是基于高达1GHz的Sitara™ARM Cortex-A8 32位RISC处理器的工业通信引擎(ICE),具有增强的图像和图形处理,外设和工业接口选择如EtherCAT和PROFIBUS,支持高等级操作系统(HLOS)

TI公司的AM3359是基于高达1GHz的Sitara™ARM Cortex-A8 32位RISC处理器的工业通信引擎(ICE),具有增强的图像和图形处理,外设和工业接口选择如EtherCAT和PROFIBUS,支持高等级操作系统(HLOS)。还包含NEON™ SIMD协处理器,集成了32KB L1指令和32KB数据缓存,256KB ECC L2缓存,176KB引导ROM,64KB专用RAM,仿真和调试-JTAG,多达128个中断请求的中断控制器,64KB通用片上存储器控制器(OCMC)RAM,主要用在游戏外设,家庭和工业自动化,消费类医疗设备,打印机和智能收费系统。本文介绍了AM3359主要特性,功能框图以及EtherCAT通信开发平台TIDEP0001主要特性,电路图和材料清单。

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image,graphics processing, peripherals and industrial interface opTIons such as EtherCAT and PROFIBUS. Thedevices support high-level operaTIng systems (HLOS)。 Processor SDK Linux and TI-RTOS are availablefree of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a briefdescription of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of eachfollows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVRSGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gamingeffects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greaterefficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocolssuch as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.

Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and allsystem-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specializeddata handling operations, custom peripheral interfaces, and in offloading tasks from the other processorcores of SoC.

AM3359主要特性:

• Up to 1-GHz Sitara™ ARM Cortex-A8 32‑BitRISC Processor

– NEON™ SIMD Coprocessor

– 32KB of L1 Instruction and 32KB of Data CacheWith Single-Error Detection (Parity)

– 256KB of L2 Cache With Error Correcting Code(ECC)

– 176KB of On-Chip Boot ROM

– 64KB of Dedicated RAM

– Emulation and Debug - JTAG

– Interrupt Controller (up to 128 InterruptRequests)

• On-Chip Memory (Shared L3 RAM)

– 64KB of General-Purpose On-Chip MemoryController (OCMC) RAM

– Accessible to All Masters

– Supports Retention for Fast Wakeup

• External Memory Interfaces (EMIF)

– mDDR(LPDDR), DDR2, DDR3, DDR3LController:

– mDDR: 200-MHz Clock (400-MHz Data Rate)

– DDR2: 266-MHz Clock (532-MHz Data Rate)

– DDR3: 400-MHz Clock (800-MHz Data Rate)

– DDR3L: 400-MHz Clock (800-MHz DataRate)

– 16-Bit Data Bus

– 1GB of Total Addressable Space

– Supports One x16 or Two x8 Memory DeviceConfigurations

– General-Purpose Memory Controller (GPMC)

– Flexible 8-Bit and 16-Bit AsynchronousMemory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-BitECC

– Uses Hamming Code to Support 1-Bit ECC

– Error Locator Module (ELM)

– Used in Conjunction With the GPMC toLocate Addresses of Data Errors fromSyndrome Polynomials Generated Using aBCH Algorithm

– Supports 4-, 8-, and 16-Bit per 512-ByteBlock Error Location Based on BCHAlgorithms

• Programmable Real-Time Unit Subsystem andIndustrial Communication Subsystem (PRU-ICSS)

– Supports Protocols such as EtherCAT,PROFIBUS, PROFINET, EtherNet/IP™, and

More

– Two Programmable Real-Time Units (PRUs)

– 32-Bit Load/Store RISC Processor Capableof Running at 200 MHz

– 8KB of Instruction RAM With Single-ErrorDetection (Parity)

– 8KB of Data RAM With Single-Error Detection(Parity)

– Single-Cycle 32-Bit Multiplier With 64-BitAccumulator

– Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal

– 12KB of Shared RAM With Single-ErrorDetection (Parity)

– Three 120-Byte Register Banks Accessible byEach PRU

– Interrupt Controller (INTC) for Handling SystemInput Events

– Local Interconnect Bus for Connecting Internaland External Masters to the Resources Insidethe PRU-ICSS

– Peripherals Inside the PRU-ICSS:

– One UART Port With Flow Control Pins,Supports up to 12 Mbps

– One Enhanced Capture (eCAP) Module

– Two MII Ethernet Ports that Support IndustrialEthernet, such as EtherCAT

– One MDIO Port

• Power, Reset, and Clock Management (PRCM)Module

– Controls the Entry and Exit of Stand-By an十大线上网赌网站dDeep-Sleep Modes

– Responsible for Sleep Sequencing, PowerDomain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-OnSequencing

– Clocks

– Integrated 15- to 35-MHz High-FrequencyOscillator Used to Generate a Reference

Clock for Various System and PeripheralClocks

– Supports Individual Clock Enable and DisableControl for Subsystems and Peripherals toFacilitate Reduced Power Consumption

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